In a semiconductor test process, a conductivity test is sometimes performed to detect a defective product by bringing probes having conductivity (conductive probes) into contact with a semiconductor wafer before dicing (WLT: Wafer Level Test). When this WLT is performed, to transfer a signal for a test generated and sent by a testing device (tester) to the semiconductor wafer, a probe card including a large number of probes is used. In the WLT, the probes are individually brought into contact with each of dies on the semiconductor wafer while the dies are scanned by the probe card. However, because several hundreds to several ten thousands dies are formed on the semiconductor wafer, it takes considerable time to test one semiconductor wafer. Thus, an increase in the number of dies causes higher cost.
To solve the problems of the WLT, recently, a method called FWLT (Full Waver Level Test) is also used in which several hundreds to several ten thousands probes are collectively brought into contact with all or at least a quarter to a half of dies on a semiconductor wafer. To accurately bring the probes into contact with electrode pads on the semiconductor wafer, technologies for maintaining positional accuracy of tips of probes by accurately keeping the parallelism or the flatness of a probe card with respect to a predetermined reference surface and for highly accurately aligning a semiconductor wafer are known in this method (see, for example, Patent Document 1 or 2).
FIG. 11 is a diagram schematically showing an example of the structure of a probe card applied in the FWLT. A probe card 8 shown in FIG. 11 includes a plurality of probes 9 provided according to an arrangement pattern of the electrode pads on a semiconductor wafer, a probe head 81 that houses the probes 9, a space transformer 82 that transforms an interval of a fine wiring pattern in the probe head 81, an interposer 83 for connection of wires led out from the space transformer 82, a substrate 84 that connects wires through the interposer 83 to a testing device, a male connector 85 provided on the substrate 84 and connected to a female connector provided on the testing device side, and a reinforcing member 86 for reinforcing the substrate 84.
Among these components, as the interposer 83, the one having a thin-film base material made of an insulating material such as ceramic and a plurality of leaf-spring connection terminals disposed in a predetermined pattern on both sides of the base material and formed in a cantilever shape is known. In the case of this interposer, connection terminals provided on one surface of the interposer 83 come into contact with electrode pads of the space transformer 82 and connection terminals provided on the other surface come into contact with electrode pads of the substrate 84, whereby electrical connection is established between the space transformer 74 and the substrate 77.
Patent Document 1: Japanese Patent No. 3386077
Patent Document 2: Japanese Patent Application Laid-open No. 2005-164600